1. Field of the Invention
The present invention relates to a very suitable driving method for a semiconductor display device using a display medium such as liquid crystals, and to a semiconductor display device which performs display using the driving method. In particular, the present invention relates to a method of driving an active matrix liquid crystal display device, and to an active matrix liquid crystal display device which performs display using the driving method.
2. Description of the Related Art
Techniques of manufacturing an element formed using a semiconductor thin film on an insulating substrate, a thin film transistor (TFT) for example, have been rapidly developing in recent years. The reason for the demand is that the demand for semiconductor display devices (typically active matrix liquid crystal display devices) has risen.
Active matrix liquid crystal display devices display an image by controlling electric charges applied to several hundreds of thousands to several millions of pixels, arranged in a matrix shape, with pixel switching elements (pixel TFTs) structured by TFTs.
Note that, throughout this specification, pixels are mainly structured by a switching element, a pixel electrode connected to the switching element, an opposing electrode, and liquid crystal formed between the pixel electrode and the opposing electrode.
A general example of the display operation of an active matrix liquid crystal display device is explained simply below with reference to FIGS. 20A and 20B. FIG. 20A is a top view of a liquid crystal panel, and FIG. 20B is a diagram showing pixel arrangement.
A source signal line driver circuit 701 is connected to source signal lines S1 to S6. Further, a gate signal line driver circuit 702 is connected to gate signal lines G1 to G4. A plurality of pixels 703 are formed in portions surrounded by the source signal lines S1 to S6 and the gate signal lines G1 to G4. Pixel TFTs 704 and pixel electrodes 705 are formed in the pixels 703. Note that the number of source signal lines and the number of gate signal lines are not limited to these values.
A display signal is inputted to the source signal line S1 in accordance with a signal from a circuit such as a shift register (not shown in the figures) within the source signal line driver circuit 701. Further, the gate signal line G1 is selected in accordance with a selection signal inputted to the gate signal line G1 from the gate signal line driver circuit 702, and the pixel TFT 704 of a pixel (1,1), at which the gate signal line G1 and the source signal line S1 intersect, turns on. The display signal inputted to the source signal line S1 is then inputted to the pixel electrode 705 of the pixel (1,1) through the pixel TFT 704. The liquid crystal is driven in accordance with the electric potential of the inputted display signal, the amount of transmitted light is controlled, and a portion of an image (the image corresponding to the pixel (1,1)) is displayed in the pixel (1,1).
Next, with the state, in which the portion of the image in the pixel (1,1) is displayed, maintained by means such as a storage capacitor (not shown in the figures), a display signal is inputted to the source signal line S2 in the next instant in accordance with a signal from the shift register or the like (not shown in the figures) within the source signal line driver circuit 701. Note that the storage capacitor is a capacitor for storing the electric potential of the display signal inputted to the gate electrode of the pixel TFT 704 for a fixed period.
The gate signal line G1 is maintained as is, selected, and the pixel TFT 704 of a pixel (1,2), at which the gate signal line G1 and the source signal line S2 intersect, turns on. The image signal inputted to the source signal line S2 is then inputted to the pixel electrode 705 of the pixel (1,2) through the pixel TFT 704. The liquid crystal is then driven in accordance with the electric potential of the inputted display signal, the amount of light transmitted is controlled, and a portion of the image (the image corresponding to the pixel (1,2)) is displayed in the pixel (1,2), similar to the pixel (1,1).
The above display operations are performed one after another, and portions or the image are displayed in succession in all of the pixels (1,1), (1,2), (1,3), (1,4), (1,5), and (1,6) connected to the gate signal line G1. The gate signal line G1 continues to be selected in accordance with the selection signal inputted to the gate signal line G1 during this period.
The gate signal line G1 is deselected when the display signal is inputted to all of the pixels connected to the gate signal line G1. Continuing, the gate signal line G2 is selected in accordance with a selection signal inputted to the gate signal line G2. Portions of the image are then displayed in succession in all of the pixels (2,1), (2,2), (2,3), (2,4), (2,5), and (2,6) connected to the gate signal line G2. The gate signal line G2 continues to be selected during this period.
One image is displayed in a pixel portion 706 by repeating the above stated operations for all of the gate signal lines. A period in which the one image is displayed is referred to as one frame period. The period during which one image is displayed in the pixel portion 706, and a vertical return period may also be taken together as the frame period. All of the pixels are maintained in a state of displaying the image by means such as a storage capacitor (not shown in the figures) until the pixel TFT of each pixel is again turned on.
In a liquid crystal panel using a component such as a TFT as a switching element, the polarity of the electric potential of the signal inputted to each pixel is normally inverted (alternating current drive) with the electric potential of the opposing electrode (common electric potential) as a standard in order to prevent degradation of the liquid crystal. Frame inverting drive, source line inverting drive, gate line inverting drive, and dot inverting drive can be given as methods of alternating current drive. Each of the driving methods is explained below.
A polarity pattern of a display signal inputted to each pixel in frame inverting drive is shown in FIG. 21A (hereafter referred to simply as a polarity pattern). Note that, with a common electric potential as a standard. “+” is shown when an electric potential of a display signal inputted to a pixel is positive, while “−” is shown when an electric potential of a display signal inputted to a pixel is negative in the figures showing polarity patterns in this specification (FIGS. 21A to 21D, FIG. 2, FIG. 4, FIG. 5, FIG. 6, and FIG. 7). Further, the polarity patterns shown in FIGS. 21A to 21D correspond to the pixel arrangement shown in FIG. 20B.
Note that, throughout this specification, a display signal having a positive polarity denotes a display signal having an electric potential which is higher than the common electric potential. Further, a display signal having a negative polarity denotes a display signal having an electric potential which is lower than the common electric potential.
Regarding a method of scanning, there is: interlaced scanning in which scanning is divided into two times (two fields), one for odd numbered gate signal lines and one for even numbered gate signal lines; and non-interlaced scanning in which the odd numbered and even numbered gate signal lines are scanned in order without being divided, in one image (one frame). Examples in which mainly non-interlaced scanning is used are explained here.
With frame inverting drive, the display is performed so that display signals having, an identical polarity are inputted to all of the pixels within one arbitrary frame period (polarity pattern 1), and the polarity of the display signals inputted to all of the pixels is inverted in the next frame period (polarity pattern 2). Namely, focusing on only the polarity pattern, the frame inverting drive is a driving method in which two types of polarity patterns (the polarity pattern 1 and the polarity pattern 2) are repeated every other frame period and the display is performed.
Source line inverting drive is explained next. Polarity patterns of pixels in the source line inverting drive are shown in FIG. 21B.
With source line inverting drive, display signals having the same polarity are inputted to all pixels connected to the same source signal line in one arbitrary frame period as shown in FIG. 21B, and display signals having the inverse polarity are inputted to pixels connected to adjacent source signal lines.
Note that, in this specification, pixels connected to a source line denotes pixels having pixel TFTs in which a source region or a drain region is connected to the source signal line.
Then, in the next frame period, display signals having the polarity that is the reverse of the display signals inputted in the previous one frame period, are inputted to each source signal line. Therefore, if a polarity pattern in an arbitrary frame period is taken as polarity pattern 3, then the polarity pattern in the next frame period becomes polarity pattern 4.
Gate line inverting drive is explained next. Polarity patterns in gate line inverting drive are shown in FIG. 21C.
As shown in FIG. 21C, display signals having the same polarity are inputted to all pixels connected to the same gate signal line during one arbitrary frame period in gate line inverting drive, and display signals having the reverse polarity are inputted to pixels connected to adjacent gate signal lines.
Note that, in this specification, pixels connected to a gate signal line denotes pixels having pixel TFTs whose gate electrode is connected to the gate signal line.
Then, in the next frame period, display signals having the inverse polarity to the display signals inputted in the previous frame period are inputted to pixels connected to each gate signal line. Therefore, if a polarity pattern in one arbitrary frame period is taken as polarity pattern 5, then the polarity pattern in the next frame period becomes frame pattern 6.
In other words, similar to source line inverting drive, the gate line inverting drive is a driving method in which two types of polarity patterns (polarity pattern 5 and polarity pattern 6) are repeated every other frame period, and display is performed.
Dot inverting drive is explained next. Polarity patterns in dot inverting drive are shown in FIG. 21D.
Dot inverting drive is a driving method in which the polarity of display signals inputted to the pixels is inverted for all adjacent pixels, as shown in FIG. 21D. Then, in one arbitrary frame period, display signals having polarities which are inverse to those of the previous frame period are inputted to each pixel. Therefore, if the polarity pattern occurring in one arbitrary frame period is taken as polarity pattern 7, then the polarity pattern of the next frame period becomes polarity pattern 8. In other words, the dot inverting drive is a driving method in which two types of polarity patterns are repeated every other frame period and display is performed.
The above alternating current drives are useful methods for preventing deterioration of the liquid crystal. However, when using the above alternating current drives, the screen flickers, and vertical striping or horizontal striping is visible.
It is considered that this is because the screen brightness differs subtly between inputted display signals of the positive polarity and those the negative polarity when performing the same gray-scale display in each pixel. This phenomenon is explained in detail below taking frame inverting drive as an example.
A timing chart when performing frame inverting drive for the active matrix liquid crystal display device of FIGS. 20A and 20B is shown in FIG. 22. Note that FIG. 22 is a timing chart of a case in which white display is performed provided that the liquid crystal display device is normally black, and black display is performed when normally white. A period during which a selection signal is inputted to one gate signal line is taken as one line period, and a period during which the selection signal is inputted to all gate signal lines and one image is displayed is taken as one frame period.
When a display signal and a selection signal are inputted to the source signal line S1 and the gate signal line G1, respectively, a display signal of a positive polarity is inputted to the pixel (1,1) provided in a portion at which the source signal line S1 and the gate signal line G1 intersect. Note that, in this specification, a display signal being inputted to a pixel denotes the display signal being inputted to the pixel electrode through the pixel TFT. The electric potential applied to the pixel electrode in accordance with the inputted display signal then ideally continues to be maintained throughout one frame period by means such as a storage capacitor.
In practice, however, if the electric potential of the gate signal line G1, when one line period is completed, shifts to an electric potential which makes the pixel TFT to be turned off, the electric potential of the pixel electrode may also be caused to change by an amount ΔV in the direction of the shift of the electric potential of the gate signal line G1. This phenomenon is referred to as field-through, and ΔV is referred to as penetration voltage.
The voltage ΔV is given by the following equation:ΔV=V×Cgd/(Cgd+Clc+Cs).  [Eqn. 1]
Note that V is the amplitude of the electric potential of the gate electrode. Cgd is the capacitance between the gate electrode and the drain region of the pixel TFT. Clc is the capacitance of the liquid crystal between the pixel electrode and the opposing electrode, and Cs is the capacitance of the storage capacitor.
In the timing chart of FIG. 22, the actual electric potential of the pixel electrode in the pixel (1,1) is shown by a solid line, and the electric potential of an ideal pixel electrode in which field-through is not considered is shown by a dotted line. In the first frame period, a display signal of a positive polarity is input to the pixel (1,1). The electric potential or the ante signal line changes to negative at the same time as the first line period is completed in the case of the first frame period shown in FIG. 22, and the electric potential of the pixel electrode of the pixel (1,1) also in practice changes in the negative direction by the amount of penetration voltage. Note that the penetration voltage in the first frame period is denoted by ΔV1 in FIG. 22.
Next, in a first line period of a second frame period, a display signal having a negative polarity, the inverse of the polarity of the first line period of the first frame period, is inputted to the pixel (1,1). When the first line period in the second frame period is then complete, the electric potential of the gate signal line G1 then changes in the negative direction. At the same time, the pixel electrode electric potential of the pixel (1,1) also changes in the negative direction by the amount of penetration voltage. Note that the penetration voltage in the second frame period is denoted by ΔV2 in FIG. 22.
The driver voltage after completion of the first line period of the first frame period is denoted by V1, and the driver voltage after completion of the first line period of the second frame period is denoted by V2 in FIG. 22. Note that, in this specification, driver voltage refers to the potential difference between the electric potential of a pixel electrode and the common electric potential.
The driver voltage V1 and the driver voltage V2 have the difference of ΔV1+ΔV2. The screen brightness of the pixel (1,1) therefore differs between the first frame period and the second frame period.
A method of reducing a value of the common electric potential has also be considered in order that the driver voltage V1 and the driver voltage V2 will become the same.
However, the capacitance Cgd between the gate electrode and the drain region oft the pixel TFT differs between when a display signal having a positive polarity is inputted to the pixel and when a display signal having a negative polarity is inputted to the pixel. In addition, the capacitance Clc of the liquid crystal between the pixel electrode and the opposing electrode fluctuates in accordance with the electric potential of the display signal inputted to the pixel. The values of Cgd and Clc thus differ in accordance with each frame period, and therefore the value of the penetration voltage ΔV also differs for each frame period. Consequently, even if the value of the common electric potential is changed, the driver voltage in the pixel (1,1) differs in accordance with the frame period, and as a result, the screen brightness differs.
This is a phenomenon which is not limited to the pixel (1,1), and occurs in all of the pixels, and the brightness of the pixels differs according to the polarity of the display signal inputted to the pixels.
With frame inverting drive, therefore, the brightness of an image displayed in the first frame period and that of an image displayed in the second frame period differ, and this is seen as flicker by an observer. In particular, a remarkable amount of flicker has been confirmed in intermediate gray-scale display.
The display brightness of pixels into which a display signal of a positive polarity is inputted also differs from that of pixels into which a display signal of a negative polarity is inputted, in cases of source line inverting drive, gate line inverting drive, and dot inverting drive.
As a result, vertical stripes are displayed on the screen by source line inverting drive, and horizontal stripes are displayed on the screen by gate line inverting drive. Further, vertical stripes and horizontal stripes appear with dot inverting drive depending upon the image displayed in the screen.
It is considered that increasing the frame frequency is effective in preventing observable screen flicker, and vertical and horizontal striping due to alternating current from being seen. However, it is necessary to increase the driving frequency of the driver circuit, in particular the driving frequency of the source signal line driver circuit, in order to increase the frame frequency. If the driving frequency of the source signal line driver circuit is then increased, there is the possibility that the operating speed of the TFTs of the source signal line driver circuit is unable to respond to the driving frequency of the source signal line driver circuit, and operation thus becomes impossible, or difficulties arise relating to reliability.